This invention relates to generating clock phases, more particularly, generating clock phases at a predetermined time, synchronized to a system clock, that to first order are independent of process parameters including drive current, parasitic resistance and parasitic capacitance, and only relative to the system clock and dependent on the system clock logic phase width and the units ratio of capacitance values.
Internal and external functional timings of embedded circuit blocks used within chipset products are characterized as needed for new silicon process technologies. Many of such timings are used in embedded memory circuit blocks. In an effort to mitigate process dependence of internal and external functional timings, xe2x80x9cclockedxe2x80x9d functions are being utilized in place of xe2x80x9cself-timedxe2x80x9d functions. However, when converting self-timed functions to clocked functions within embedded circuit blocks, providing a clock signal that is a multiple value of the system clock with adequate timing margin adds complexity. For example, a circuit may simply require a single clock phase delayed from the system clock by a fixed amount of time, or may require a multiplied clock signal. Typically, such a signal is provided by a self-timed xe2x80x9cdelay chainxe2x80x9d. A delayed phase may also be generated by a higher order clock signal from a phase locked loop (PLL), and routed to the embedded block. Other schemes for generating synchronous clock phases and clock multiplication are utilized, including load modulated inverter delay chains and delay locked loops (DLL).